(a) Fields of the Invention
The present invention relates to semiconductor integrated circuit devices in which logic circuits or logic circuits and memory circuits are integrated in one semiconductor chip and which are provided with nonvolatile memory elements as alternatives to fuse elements incorporated into the semiconductor integrated circuit device and determining operations of the circuits after fabrication of the device, particularly such as redundancy repair, functional expansion, or functional modification, and to methods for testing such a device.
(b) Description of Related Art
In recent large scale integrated circuits (LSI), an increase in circuit scale thereof and complication of functions incorporated therein are remarkable. As the speeds of data processing and signal processing are enhanced, the capacity of a memory integrated in an LSI increases irrespective of memory type. With this increase, it becomes necessary to make modification of the state of a semiconductor integrated circuit device by fuse elements after completion of fabrication of the device as a product, such as redundancy repair of memories, expansion or modification of logic functions, accuracy adjustment of analog circuits, and such a necessity tends to increase irrespective of the scale and the accuracy of the device.
The increase in the conventional adjustment functions made by fuse elements, however, increases the number of fuse elements, resulting in an increase in total area of the fuse elements on a semiconductor chip. Moreover, the semiconductor device has many restrictions against the fuse elements, such as that a metal interconnect cannot be provided in a layer above the fuse element.
As a solution of this disadvantage, a nonvolatile memory cell capable of being configured by a normal CMOS process without using the adjustment functions by fuse elements is shown in, for example, Japanese Patent Publication No. 2667099. This nonvolatile memory cell is formed by a CMOS process, composed of two transistors differing in conductivity type and having a common gate, and configured so that one transistor thereof is used as a control gate and the other transistor is used for input and output. That is to say, the common gate of the two transistors functions as a floating gate of a commonly used electronically erasable and programmable read only memory (EEPROM), thereby attaining a nonvolatile memory device.
An approach to improving the reliability of the nonvolatile memory device of CMOS configuration by differentially amplifying the device is shown in, for example, Japanese Patent Publication No. 3090329.
The most advanced semiconductor process at present is a fine process whose design rule is as small as about 0.13 μm. Moreover, a member constituting a transistor, for example, a gate insulating film has a reduced film thickness. Under such a circumstance, even if a MOS transistor is simply shrunk with the structure thereof kept, leakage current occurring in the shrunk MOS transistor increases, resulting in trouble with the long-term reliability of the transistor.
In addition, nonvolatile memory elements functioning as fuse elements also have a function that must be realized besides the long-term reliability.
To be more specific, in the case of using a fuse element, either the short-circuit state or the floating state appears uniquely between two terminals of the fuse element regardless of whether the fuse is made of metal or polysilicon.
In contrast to this, in the case of using one nonvolatile memory element and an amplifier or a differential amplifier for this element, the state of charge accumulation of a floating gate constituting the nonvolatile memory element of CMOS configuration is not always determined uniquely because it depends on a process in device fabrication.
Moreover, in the case of employing a differential amplifier, two nonvolatile memory elements connected to the differential amplifier are equal in floating gate potential, so that the two elements have almost the same threshold value Vt. This causes a problem in which an output signal from the semiconductor integrated circuit device substituting for a fuse element and having multiple differential amplifiers cannot indicate a constant output result.
Specifically, for example, in the case where this semiconductor integrated circuit device is employed for redundancy repair of a memory device such as a dynamic random access memory (DRAM), a static random access memory (SRAM), or a read only memory (ROM), it is desirable that a uniquely determined potential selects a normal memory cell and the memory space of the selected cell is tested. However, in the case where nonvolatile memory elements are employed instead of fuse elements, the output results from the nonvolatile memory elements vary to hinder even a normal performance of the test.